synopsys DWC3 CORE

DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
      as described in 'usb/generic.txt'

Required properties:
 - compatible: must be "snps,dwc3"
 - reg : Address and length of the register set for the device
 - interrupts: Interrupts used by the dwc3 controller.
 - clock-names: should contain "ref", "bus_early", "suspend"
 - clocks: list of phandle and clock specifier pairs corresponding to
           entries in the clock-names property.

Exception for clocks:
  clocks are optional if the parent node (i.e. glue-layer) is compatible to
  one of the following:
    "amlogic,meson-axg-dwc3"
    "amlogic,meson-gxl-dwc3"
    "cavium,octeon-7130-usb-uctl"
    "qcom,dwc3"
    "samsung,exynos5250-dwusb3"
    "samsung,exynos5433-dwusb3"
    "samsung,exynos7-dwusb3"
    "sprd,sc9860-dwc3"
    "st,stih407-dwc3"
    "ti,am437x-dwc3"
    "ti,dwc3"
    "ti,keystone-dwc3"
    "rockchip,rk3399-dwc3"
    "xlnx,zynqmp-dwc3"

Optional properties:
 - usb-phy : array of phandle for the PHY device.  The first element
   in the array is expected to be a handle to the USB2/HS PHY and
   the second element is expected to be a handle to the USB3/SS PHY
 - phys: from the *Generic PHY* bindings
 - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
	or "usb3-phy".
 - resets: a single pair of phandle and reset specifier
 - snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
 - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
 - snps,dis-start-transfer-quirk: when set, disable isoc START TRANSFER command
			failure SW work-around for DWC_usb31 version 1.70a-ea06
			and prior.
 - snps,disable_scramble_quirk: true when SW should disable data scrambling.
	Only really useful for FPGA builds.
 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
 - snps,lpm-nyet-threshold: LPM NYET threshold
 - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
 - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
 - snps,req_p1p2p3_quirk: when set, the core will always request for
			P1/P2/P3 transition sequence.
 - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
			amount of 8B10B errors occur.
 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
			from P0 to P1/P2/P3.
 - snps,lfps_filter_quirk: when set core will filter LFPS reception.
 - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
			Polling LFPS after RX.Detect.
 - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
			LTSSM during USB3 Compliance mode.
 - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
 - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
 - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG,
			disabling the suspend signal to the PHY.
 - snps,dis-u1-entry-quirk: set if link entering into U1 needs to be disabled.
 - snps,dis-u2-entry-quirk: set if link entering into U2 needs to be disabled.
 - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
			in PHY P3 power state.
 - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists
			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
			a free-running PHY clock.
 - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power
			from P0 to P1/P2/P3 without delay.
 - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
			during HS transmit.
 - snps,parkmode-disable-ss-quirk: when set, all SuperSpeed bus instances in
			park mode are disabled.
 - snps,dis_metastability_quirk: when set, disable metastability workaround.
			CAUTION: use only if you are absolutely sure of it.
 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
			utmi_l1_suspend_n, false when asserts utmi_sleep_n
 - snps,hird-threshold: HIRD threshold
 - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
   UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
 - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
	register for post-silicon frame length adjustment when the
	fladj_30mhz_sdbnd signal is invalid or incorrect.
 - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode
			only. Set this and rx-max-burst-prd to a valid,
			non-zero value 1-16 (DWC_usb31 programming guide
			section 1.2.4) to enable periodic ESS RX threshold.
 - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set
			this and rx-thr-num-pkt-prd to a valid, non-zero value
			1-16 (DWC_usb31 programming guide section 1.2.4) to
			enable periodic ESS RX threshold.
 - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode
			only. Set this and tx-max-burst-prd to a valid,
			non-zero value 1-16 (DWC_usb31 programming guide
			section 1.2.3) to enable periodic ESS TX threshold.
 - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set
			this and tx-thr-num-pkt-prd to a valid, non-zero value
			1-16 (DWC_usb31 programming guide section 1.2.3) to
			enable periodic ESS TX threshold.

 - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
 - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
			register, undefined length INCR burst type enable and INCRx type.
			When just one value, which means INCRX burst mode enabled. When
			more than one value, which means undefined length INCR burst type
			enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.

 - in addition all properties from usb-xhci.txt from the current directory are
   supported as well


This is usually a subnode to DWC3 glue to which it is connected.

dwc3@4a030000 {
	compatible = "snps,dwc3";
	reg = <0x4a030000 0xcfff>;
	interrupts = <0 92 4>
	usb-phy = <&usb2_phy>, <&usb3,phy>;
	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
