* Amlogic AXG Audio Clock Controllers

The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.

Required Properties:

- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,
		  "amlogic,g12a-audio-clkc" for G12A.
- reg		: physical base address of the clock controller and length of
		  memory mapped region.
- clocks	: a list of phandle + clock-specifier pairs for the clocks listed
		  in clock-names.
- clock-names	: must contain the following:
		  * "pclk" - Main peripheral bus clock
		  may contain the following:
		  * "mst_in[0-7]" - 8 input plls to generate clock signals
		  * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
				      components.
		  * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
				       components.
- resets	: phandle of the internal reset line
- #clock-cells	: should be 1.
- #reset-cells  : should be 1 on the g12a (and following) soc family

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
used in device tree sources.

Example:

clkc_audio: clock-controller@0 {
	compatible = "amlogic,axg-audio-clkc";
	reg = <0x0 0x0 0x0 0xb4>;
	#clock-cells = <1>;

	clocks = <&clkc CLKID_AUDIO>,
		 <&clkc CLKID_MPLL0>,
		 <&clkc CLKID_MPLL1>,
		 <&clkc CLKID_MPLL2>,
		 <&clkc CLKID_MPLL3>,
		 <&clkc CLKID_HIFI_PLL>,
		 <&clkc CLKID_FCLK_DIV3>,
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_GP0_PLL>;
	clock-names = "pclk",
		      "mst_in0",
		      "mst_in1",
		      "mst_in2",
		      "mst_in3",
		      "mst_in4",
		      "mst_in5",
		      "mst_in6",
		      "mst_in7";
	resets = <&reset RESET_AUDIO>;
};
