* Cadence PCIe host controller

This PCIe controller inherits the base properties defined in
host-generic-pci.txt.

Required properties:
- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
- reg: Should contain the controller register base address, PCIe configuration
  window base address, and AXI interface region base address respectively.
- reg-names: Must be "reg", "cfg" and "mem" respectively.
- #address-cells: Set to <3>
- #size-cells: Set to <2>
- device_type: Set to "pci"
- ranges: Ranges for the PCI memory and I/O regions
- #interrupt-cells: Set to <1>
- interrupt-map-mask and interrupt-map: Standard PCI properties to define the
  mapping of the PCIe interface to interrupt numbers.

Optional properties:
- cdns,max-outbound-regions: Set to maximum number of outbound regions
  (default 32)
- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the
  number of least significant bits kept during inbound (PCIe -> AXI) address
  translations (default 32)
- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
- device-id: The PCI device ID (16 bits, default is design dependent)
- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
  than one in the list.  If only one PHY listed it must manage all lanes. 
- phy-names:  List of names to identify the PHY.

Example:

pcie@fb000000 {
	compatible = "cdns,cdns-pcie-host";
	device_type = "pci";
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x0 0xff>;
	linux,pci-domain = <0>;
	cdns,max-outbound-regions = <16>;
	cdns,no-bar-match-nbits = <32>;
	vendor-id = /bits/ 16 <0x17cd>;
	device-id = /bits/ 16 <0x0200>;

	reg = <0x0 0xfb000000  0x0 0x01000000>,
	      <0x0 0x41000000  0x0 0x00001000>,
	      <0x0 0x40000000  0x0 0x04000000>;
	reg-names = "reg", "cfg", "mem";

	ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
		 <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;

	#interrupt-cells = <0x1>;

	interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1
			 0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1
			 0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1
			 0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;

	interrupt-map-mask = <0x0 0x0 0x0  0x7>;

	msi-parent = <&its_pci>;

	phys = <&pcie_phy0>;
	phy-names = "pcie-phy";
};
