These bindings should be considered EXPERIMENTAL for now.

* Renesas R8A7740  Clock Pulse Generator (CPG)

The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
and several fixed ratio and variable ratio dividers.

Required Properties:

  - compatible: Must be "renesas,r8a7740-cpg-clocks"

  - reg: Base address and length of the memory resource used by the CPG

  - clocks: Reference to the three parent clocks
  - #clock-cells: Must be 1
  - clock-output-names: The names of the clocks. Supported clocks are
    "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
    "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".

  - renesas,mode: board-specific settings of the MD_CK* bits


Example
-------

cpg_clocks: cpg_clocks@e6150000 {
        compatible = "renesas,r8a7740-cpg-clocks";
        reg = <0xe6150000 0x10000>;
        clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
        #clock-cells = <1>;
        clock-output-names = "system", "pllc0", "pllc1",
                             "pllc2", "r",
                             "usb24s",
                             "i", "zg", "b", "m1", "hp",
                             "hpp", "usbp", "s", "zb", "m3",
                             "cp";
};

&cpg_clocks {
	renesas,mode = <0x05>;
};
